1. Field of the Invention
The present invention relates to a digital filter and an operation method in the digital filter, and more particularly to a cosine roll-off filter and an operation method in the filter.
2. Description of the Prior Art
Generally, a cosine roll-off filter is used to adjust a rectangular wave so as to bring its waveform into a position corresponding to a multiple of the number of taps to prevent interference due to reflection when transmitting it.
FIG. 3 shows a configuration of a conventional digital filter. In the figure, a general 5-tap FIR-type filter is shown. Specifically, multipliers M1 to M5 are provided corresponding to coefficients C1 to C5 inputted from five taps, and outputs of the multipliers M1 to M5 are added by adders A1 to A4 to obtain a final output. Input data to the filter is successively sent to subsequent stages by four flip-flops (hereinafter simply referred to as F/F) 31 to 34.
Consider the use of the filter of FIG. 3 in a double sampling mode. For input data of D1, D2, D3, . . . , D5, a filter output is as shown below. That is, output Y1 by the double sampling and output Y2 obtained one half cycle later are as follows.
xe2x80x83Output Y1=D1xc3x97(C5+C4)+D2xc3x97(C3+C2)+D3xc3x97C1
Output Y2=D1xc3x97C5+D2xc3x97(C4+C3)+D3xc3x97(C2+C1)xe2x80x83xe2x80x83(1)
Furthermore, when the filter is used as a cosine roll-off filter, since C5=C1 and C4=C2 are satisfied because of symmetry, the above expression (1) is replaced by:
Output Y1=D1xc3x97(C1+C2)+D2xc3x97(C3+C2)+D3xc3x97C1
Output Y2=D1xc3x97C1+D2xc3x97(C3+C2)+D3xc3x97(C1+C2)xe2x80x83xe2x80x83(2)
It is to be noted that the coefficients C1, (C1+C2), and (C2+C3) are common in both the expressions (1) and (2).
Accordingly, by sharing overlapping hardware portions in FIG. 3 so that tap coefficients da1, da2, and da3 are equal to C1+C2, C2+C3, and C1, respectively, a filter can be realized which is identical in function and about half in the number of components with respect to the FIR-type filter of the figure. The realized filter is shown in FIG. 4.
In the figure, with multipliers M1 to M3 provided corresponding to coefficients da1 to da3 inputted from three taps, outputs of the multipliers M1 to M3 are temporarily stored in F/Fs 41 to 44 and are added by adders A1 to A4. A final output is obtained by switching an output selector 40.
In FIG. 4, an operating speed and the number of components are significantly reduced by integrating tap coefficients between oversamplings, taking advantage of the fact that input data is unchanged for the duration of oversampling in the double sampling mode.
Furthermore, with the filter, the speed of the multipliers commonly considered to have the lowest operating speed may be half that of those in FIG. 3, contributing to speedup.
Next, consider quadruple sampling in the filter of FIG. 5. In FIG. 5, with multipliers M1 to M9 provided corresponding to coefficients C1 to C9 inputted from nine taps, outputs of the multipliers M1 to M9 are added by adders A1 to A8 to obtain a final output. Input data to the filter is successively sent to subsequent stages by four flip-flops (F/F) 515o 58.
In this case, as in the expressions (1) and (2), for input data of Dl, D2, D3, and so forth, filter output is as shown below. Specifically, output Y1 by the quadruple sampling, output Y2 obtained a quarter of the cycle later, output Y3 obtained a quarter of that cycle later, and output Y4 obtained a quarter of that cycle later satisfy the following expression.
Y1=D1xc3x97(C9+C8+C7+C6)+D2xc3x97(C5+C4+C3+C2)+D3xc3x97C1
Y2=D1xc3x97(C9+C8+C7)+D2xc3x97(C6+C5+C4+C3)+D3xc3x97(C2+C1)
Y3=D1xc3x97(C9+C8)+D2xc3x97(C7+C6+C5+C4)+D3xc3x97(C3+C2+C1)
xe2x80x83Y4=D1xc3x97C9+D2xc3x97(C8+C7+C6+C5)+D3xc3x97(C4+C3+C2+C1)xe2x80x83xe2x80x83(3)
where if C1=C9, C2=C8, C3=C7, and C4=C6,
Y1=D1xc3x97(C1+C2+C3+C4)+D2xc3x97(C2+C3+C4+C5)+D3xc3x97C1
Y2=D1xc3x97(C1+C2+C3)+D2xc3x97(C3+C4+C4+C5)+D3xc3x97(C1+C2)
Y3=D1xc3x97(C1+C2)+D2xc3x97(C3+C4+C4+C5)+D3xc3x97(C1+C2+C3)
Y4=D1xc3x97C1+D2xc3x97(C2+C3+C4+C5)+D3xc3x97(C1+C2+C3+C4)xe2x80x83xe2x80x83(4)
Accordingly, as in FIG. 4, an FIR-type filter of FIG. 6 can be obtained by sharing overlapping hardware portions in FIG. 5.
Tap coefficients ka1, ka2, ka3, kb1, kb2, and kb3 are equal to C1+C2+C3+C4, C2+C3+C4+C5, C1, C1+C2+C3, C3+C4+C4+C5, and C1+C2, respectively.
In the figure, with multipliers M11 to M13 provided corresponding to coefficients ka1 to ka3 inputted from three taps, outputs of the multipliers M11 to M13 are temporarily stored in F/Fs 611 to 614 and are added by adders A11 to A14.
A counterpart of the same configuration described above is provided (portion indicated by dashed lines in the figure). Specifically, with multipliers M21 to M23 provided corresponding to coefficients kb1 to kb3 inputted from three taps, outputs of the multipliers M21 to M23 are temporarily stored in F/Fs 621 to 624 and are added by adders A21 to A24. A final output is obtained by switching an output selector 60.
In the example of FIG. 6, in 2N-times (N is a positive integer) sampling operations such as quadruple or octuple sampling, a filter can be realized which is half in the number of components and xc2xdN in multiplier operating speed with respect to normal FIR-type filters.
As described above, the prior art is described in, e.g., Japanese Published Unexamined Patent Application No. Hei 5-55875. Such a digital filter is very efficiently configured. However, to realize, e.g., a 113-tap octuple-sampling filter would require 60 multipliers and 112 adders. An example of configuration in this case is shown in FIG. 7. In the figure, a number of multipliers, adders, and F/Fs (a block indicated by a rectangle in FIG. 7) are provided corresponding to incoming coefficients fa1 to faF and fb1 to fbF, and further, a counterpart of the same configuration is provided. Therefore, there is a drawback in that a huge amount of hardware is required. Concrete expressions of the coefficients fa1 to faF and fb1 to fbF are omitted.
There is also a problem that the operating speed of a filter depends on the switching speed of a selector at the last output stage. Specifically, the operating speed of an entire filter is determined by the operating speed of the selectors 40, 60, and the like of the last output stage, making it difficult to increase an operating speed.
The present invention has been made to solve the above-described drawbacks of the prior art, and its object is to offer a digital filter that has a small amount of hardware and a high operating speed, and an operation method in the digital filter.
A digital filter according to the present invention is a digital filter including multiplying means for multiplying input data and predetermined coefficients and adding means for adding the multiplication results, comprising: N (N is a natural number) multipliers in which, of first to (2N+1)-th multiplying means, M-th (M=1 to N) multiplying means and M-th (M=N+2 to 2N+1) multiplying means are shared, and to which the input data is inputted as one of inputs; N selectors, provided corresponding to the N multipliers, for inputting first and second coefficient groups to the corresponding multipliers by time-sharing; and adding means for adding, between corresponding multipliers, the results of multiplications by the N multipliers when the first coefficient group is inputted, and the results of multiplications by the N multipliers when the second coefficient group is inputted. The adding means comprises: a first adder group for cumulatively adding the results of multiplications by the N multipliers when the first coefficient group is inputted; a second adder group for cumulatively adding the results of multiplications by the N multipliers when the second coefficient group is inputted; and output selectors for outputting the results of additions of the first and second adder groups by time-sharing. The input data changes in its contents at a first cycle and inputs of the N selectors are switched at a second cycle, which is double the first cycle. As another option, first and second holding circuit groups may be further provided corresponding to the first and second coefficient groups, respectively, such that when the second coefficient group is inputted to the N multipliers, the results of additions by the first adder group are held in the first holding circuit group, and when the first coefficient group is inputted to the N multipliers, the results of additions by the second adder group are held in the second holding circuit group.
An operation method in a digital filter according to the present invention is an operation method in a digital filter including multiplying means for multiplying input data and predetermined coefficients and adding means for adding the multiplication results, comprising: a multiplying step for performing multiplications by N (N is a natural number) multipliers in which, of first to (2N+1)-th multiplying means, M-th (M=1 to N) multiplying means and M-th (M=N+2 to 2N+1) multiplying means are shared, and to which the input data is inputted as one of inputs; a step for inputting, by N selectors provided corresponding to the N multipliers, first and second coefficient groups to the corresponding multipliers by time-sharing; and an adding step for adding, between corresponding multipliers, the results of multiplications by the N multipliers when the first coefficient group is inputted, and the results of multiplications by the N multipliers when the second coefficient group is inputted. The adding step outputs, by time-sharing, a first addition result of cumulatively adding the results of multiplications by the N multipliers when the first coefficient group is inputted, and a second addition result of cumulatively adding the results of multiplications by the N multipliers when the second coefficient group is inputted. The input data changes in its contents at a first cycle and inputs of the N selectors are switched at a second cycle, which is double the first cycle. As another option, a holding step may be further included which uses first and second holding circuit groups provided corresponding to the first and second coefficient groups, respectively such that when the second coefficient group is inputted to the N multipliers, the results of additions by the first adder group are held in the first holding circuit group, and when the first coefficient group is inputted to the N multipliers, the results of additions by the second adder group are held in the second holding circuit group.